System Configuration

Supercomputer AOBA consists of two subsystems, AOBA-A and AOBA-B.

AOBA-A is a 72-node system of NEC SX-Aurora TSUBASA, while AOBA-B is a 68-node system of NEC LX 406Rz-2. Both of the two subsystems use AMD EYPC 7702 processors. Besides, each node of AOBA-A is equipped with 8 Vector Engines Type 20B.

• Total performance: 1.78 Pflop/s
• Total memory bandwidth: 924 TB/s

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Application Development

We are working together with application developers to achieve high performance.

We have a lot of joint-research projects with application developers in various research areas. As a major supercomputing center, the Cyberscience Center has made outstanding contributions to various research fields, such as Airplane and Turbine simulations for engineering, Tsunami inundation and flood simulations for disaster prevention and reduction, and heat stroke risk simulation for public health.

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Code Optimization by Machine Learning

Can ML replace a "Superprogrammer"?

Conventionally, high performance computing (HPC) applications are optimized for their target computing systems based on experiences of programmers. The program optimization often needs to select an appropriate implementation from multiple candidates, and the implementation selection has usually been made in a try and error fashion. Thus, there is a demand for automating the implementation selection. Recently, it is extensively reported that machine learning models can successfully replace various tasks that have empirically been done by experts. Therefore, machine learning becomes a promising approach to the automation of program optimization.

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Code Transformation for Performance Tuning

A key to success is effective collabotion between application developers and performance engineers.

System‐aware code optimizations often make it difficult for programmers to maintain HPC application codes. On the other side, system‐aware code optimizations are mandatory to exploit the performance of target HPC systems. To achieve both high maintainability and high performance, we develop the Xevolver framework that provides an easy way to express system‐aware code optimizations as user‐defined code transformation rules. Those rules can be defined separately from HPC application codes. As a result, an HPC application code is converted into its optimized version for a particular target system just before the compilation, and standard HPC programmers do not usually need to maintain the optimized version that could be complicated and difficult‐to‐maintain.

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HPC and Quantum Computing

How can the emerging devices help HPC? How can HPC help the emerging devices?

The effects that problem formulation and embedding have on the performance of a quantum annealer (QA) are not well studied. Thus we investigate these effects, determine methods through which performance can be maximized, and investigate the interplay between them. We select scheduling problems for our evaluation. Scheduling is one of the most ubiquitous types of problems in optimization and has applications in many fields. The standard form of these problems is finding an assignment of tasks to resources that satisfies problem constraints; however, real world applications require domain specific variants. In this work, we select the standard n×m job-shop scheduling problem (JSP) to evaluate the performance of QA.

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Heterogeneous Computing

Effective collaboration of different kinds of processors

Many supercomputers in recent years have accelerators specialized for scientific computation in addition to the conventional general-purpose processors (CPUs). Representative accelerators are Graphics Processing Units (GPUs) and Vector Engines (VEs). By using accelerators, many applications can obtain significant performance improvement compared with just using CPUs. Besides, since accelerators can achieve high energy efficiency, accelerator computing will be widespread and generalized even more in the future.

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Task Mapping and Scheduling

Intelligent resource management is a key to achieve high performance.

The mapping of tasks to processor cores, called task mapping, is crucial to achieving scalable performance on multicore processors. On modern NUMA (non-uniform memory access) systems, the memory congestion problem could degrade the performance more severely than the data locality problem because heavy congestion on shared caches and memory controllers could cause long latencies. Conventional work on task mapping mostly focuses on improving the locality of memory accesses. However, we showed that on modern NUMA systems, maximizing the locality can degrade the performance due to memory congestion. Therefore, we propose a task mapping method that addresses the locality and the memory congestion problems to improve the performance of parallel applications.

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Tsunami Inudation Simulation

Predicting damage from a tsunami immediately after the earthquake

TWe established a new method of real-time tsunami inundation forecasting, damage estimation and mapping with use of advanced sensor networks and modern computing power. The method consists of fusion of real-time crustal deformation monitoring/fault model estimation, high-performance real-time tsunami propagation/inundation simulation with a vector supercomputer, and tsunami fragility curves for damage/loss estimation. The method has recently accomplished “10-10-10 challenge”, to complete tsunami source determination in 10 minutes, tsunami inundation modeling in 10 minutes with 10 m grid resolution.

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Memory Architecture Design

Integrating large and fast memories into a single system

A modern computer needs a memory system with a high performance and a large capacity. The goal of this research is to achieve a Near/Far memory system that consists of memory modules with different performances and capacities. Moreover, the system appropriately organizes the application data among these modules by data access characteristics.

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Code Optimization and Tuning

Making application codes suitable for a specific architecture.

Microprocessors increase diversity due to the trends in manufacturing technologies and applications. This research evaluates various latest microprocessors and, based on the evaluation results, adopts the applications to the microprocessors by optimizing and tuning the application codes to obtain the high performances.

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